Network topology for a scalable multiprocessor system

ABSTRACT

A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

This application is a continuation of U.S. application Ser. No.09/408,972, filed on Sep. 29, 1999, which is incorporated herein byreference.

FIELD OF THE INVENTION

The present invention relates generally to the field of high-speeddigital data processing systems, and more particularly, tointerconnection topologies for interconnecting processing element nodesin multiprocessor computer systems.

BACKGROUND OF THE INVENTION

Multiprocessor computer systems comprise a number of processing elementnodes connected together by an interconnect network. Each processingelement node includes at least one processing element. The interconnectnetwork transmits packets of information or messages between processingelement nodes. Multiprocessor computer systems having up to hundreds orthousands of processing element nodes are typically referred to asmassively parallel processing (MPP) systems. In a typical multiprocessorMPP system, every processing element can directly address all of memory,including the memory of another (remote) processing element, withoutinvolving the processor at that processing element. Instead of treatingprocessing element-to-remote-memory communications as an I/O operation,reads or writes to another processing element's memory are accomplishedin the same manner as reads or writes to the local memory. In suchmultiprocessor MPP systems, the infrastructure that supportscommunications among the various processors greatly affects theperformance of the MPP system because of the level of communicationsrequired among processors.

Several different topologies have been proposed to interconnect thevarious processors in such MPP systems, such as rings, stars, meshes,hypercubes, and torus topologies. For example, in a conventionalhypercube network, a plurality of microprocessors are arranged in ann-dimensional cube where the number of nodes k in the network is equalto 2^(n). In this network, each node is connected to each other node viaa plurality of communications paths. The network diameter, the longestcommunications path from any one node on the network to any other node,is n-links.

Regardless of the topology chosen, one disadvantage of currentmultiprocessor systems, and in particular MPP systems, is that in orderto expand the system, a significant amount of reconfiguration isrequired. The reconfiguration often involves removing and replacingcables which is very time consuming. Also, as systems increase thenumber of processors, the number of physical connections required tosupport the system increases significantly which increases thecomplexity of the system.

Therefore, it is desired that systems could be easily scaled to increasethe number of processors with minimal disruption to the original systemconfiguration.

SUMMARY OF THE INVENTION

The present invention provides a system and method for interconnecting aplurality of processing element nodes within a scalable multiprocessorsystem. Each processing element node includes at least one processor andmemory. A scalable interconnect network includes physical communicationlinks interconnecting the processing element nodes in a cluster. A firstset of routers in the scalable interconnect network route messagesbetween the plurality of processing element nodes. One or moremetarouters in the scalable interconnect network route messages betweenthe first set of routers so that each one of the routers in a firstcluster is connected to all other clusters through one or moremetarouters.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is block diagram of a multiprocessor computer system.

FIG. 2 is a block diagram of one embodiment of the interface between ascalable interconnect network and four processing element nodes.

FIG. 3 is a model of a two dimensional (2D) hypercube topologymultiprocessor computer system.

FIG. 4 is a model of a three dimensional (3D) hypercube topologymultiprocessor computer system.

FIG. 5 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having 129 processors to 160 processors.

FIG. 6 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having 161 processors to 192 processors.

FIG. 7 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having 193 processors to 224 processors.

FIG. 8 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having 225 processors to 256 processors.

FIG. 9 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 288 processors.

FIG. 10 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 320 processors.

FIG. 11 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 352 processors.

FIG. 12 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 384 processors.

FIG. 13 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 416 processors.

FIG. 14 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 448 processors.

FIG. 15 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 480 processors.

FIG. 16 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 512 processors.

FIG. 17 illustrates an example embodiment of a multiprocessor computersystem having 512 processors.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the preferred embodiments,reference is made to the accompanying drawings which form a part hereof,and in which is shown by way of illustration specific embodiments inwhich the invention may be practiced. It is to be understood that otherembodiments may be utilized and structural or logical changes may bemade without departing from the scope of the present invention. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims.

System Overview. A representative multiprocessor computer systemaccording to the present invention is indicated generally at 20 inFIG. 1. As indicated in FIG. 1, multiprocessor computer system 20includes up to n nodes, such as indicated by a first node 22, a secondnode 24, and an nth node 26. The nodes are interconnected by a scalableinterconnect network 28, which permits multiprocessor computer systems20 to be scaled from desk side systems to very large supercomputerconfigurations.

As illustrated in detail for first node 22, each node in multiprocessorcomputer system 20 includes at least one processor, such as a firstprocessor 30 and a second processor 32 for node 22. An interface circuit34 interfaces with scalable interconnect network 28 and communicateswith a memory and directory 36 and an input/output subsystem 38.

Although the multiprocessor computer system 20 illustrated in FIG. 1provides one example environment to implement the below-describednetwork topology according to the present invention, the presentinvention is in no way limited to this particular applicationenvironment. In fact, many alternative environments using alternativenode and interface circuit configurations can be utilized. To a largeextent, the network topology according to the present invention, asimplemented in scalable interconnect network 28, is independent of thecomplexity of the nodes, such as nodes 22, 24, and 26, interconnected bythat topology.

FIG. 2 illustrates, in block diagram form, one embodiment of theinterface between a scalable interconnect network 128 and four nodes122, 123, 124, and 125. In this embodiment, scalable interconnectnetwork 128 includes one or more routers, such as the example router 150shown in FIG. 2. Router port 163 communicates with a first node 122. Asshown in the expanded view of the first node 122, router port 163communicates with the first node 122 via interface chip 134. In thefirst node 122, interface chip 134 communicates with processors 130,131, 132, and 133. Similarly, router port 164 communicates with a secondnode 123, router port 165 communicates with a third node 124, and routerport 166 communicates with a fourth node 125. Router ports 152, 154,156, and 158 communicate with other routers in the scalable interconnectnetwork 128 as further described below. In the example embodimentillustrated in FIG. 2, one router 150 communicates directly with up tosixteen processors and up to four other routers in the scalableinterconnect network 128.

The scalable interconnect network 128 of the present invention employs afirst set of routers (such as router 150 of FIG. 2) for routing messagesbetween a plurality of processing element nodes (such as nodes 122, 123,124, and 125 in FIG. 2). In one embodiment of the present invention,four of the eight ports of each one of the first set of routers arededicated to connecting from the routers to four separate nodes, such asindicated in FIG. 2. As further described below, the remaining ports areconnected to the first set of routers for routing messages between thenodes and a second set of routers (referred to herein as “metarouters”)for routing messages between the first set of routers. In oneembodiment, the metarouters shown in FIGS. 5-16 below are multiportrouters having at least four ports. One of skill in the art willrecognize that a single multiport router or any combination of multiportrouters can be used in the configurations shown in FIGS. 5-16.

As will be better understood by the following discussion, the topologyof a scalable interconnect network according to the present invention,is easily scaleable, has increased resilency and allows systemupgrades/expansion to be performed with minimal disruption to thesystem.

Example Network Topologies. A grouping of a plurality of processingelement nodes, a plurality of physical interconnections (such as cables)for connecting the plurality of processing element nodes, and a firstset of routers for routing messages between a plurality of processingelement nodes is referred to herein as a “cluster.” In a multiprocessingsystem of the present invention, each cluster is connected to each oneof the other clusters using one or more metarouters. Thus, each one ofthe clusters can communicate directly with another one of the clusterswithout having to communicate through a third cluster.

In one embodiment, the processing element nodes and first set of routersform one or more two-dimensional hypercube systems. An example twodimensional (2D) hypercube topology multiprocessor computer system isshown in FIG. 3. In FIG. 3, the four routers 150 are numbered 0 through3 and are interconnected as a 2D hypercube. In one embodiment, the 2Dhypercube comprises up to sixty-four processors because each of the fourrouters communicates with up to sixteen processors as shown in FIG. 2.In the following detailed description clusters are configured in atwo-dimensional hypercube for illustrative purposes only. The inventionis not limited to arranging the first set of routers in atwo-dimensional hypercube. Alternate embodiments in which the first setof routers are grouped in different topologies are contemplated aswithin the scope of the invention.

In one embodiment, a multiprocessor computer system is constructed withup to 128 processors without the use of metarouters. Such an embodimentis shown in FIG. 4. in which a first cluster 400 and a second cluster402 are each arranged as two-dimensional hypercubes. As shown in FIG. 4,the routers of a first cluster 400 and a second cluster 402 areinterconnected to form a three-dimensional (3D) hypercube. The 3Dhypercube is comprised of eight routers 150 numbered 0 through 7. In anexample embodiment, each one of the routers is an eight port routerconnected to four processing element nodes such as the router shown inFIG. 2. For processing element nodes having four processors each, the 3Dhypercube interconnects up to 128 processors.

Larger scale system configurations and the corresponding logicaltopologies for example systems having 128 or more processors aredescribed below. The larger scale systems employ a second set of routers(referred to herein as “metarouters”) to interconnect the clusters. Thenovel network topologies of the present invention allow two clusters tocommunicate directly without having to route messages through a thirdcluster. Rather than routing messages through a third cluster, therouters in each cluster are connected to all other clusters through themetarouters.

As shown in FIGS. 5-16, each router is either connected directly to arouter of another cluster or is connected to a router of another clusterusing one or more metarouters. In the example embodiments shown in FIGS.5-16, the connections from a single router in one cluster to routers inall other clusters are represented by particular line styles. The dashedlines in FIGS. 5-16 represent the connections from a first router in afirst cluster to a single router in each one of the other clusters. Thesolid lines in FIGS. 5-16 represent the connections from a second routerin the first cluster to a second router in each one of the otherclusters. The dotted lines in FIGS. 5-16 represent the connections froma third router in the first cluster to a third router in each one of theother clusters. The dash/dot lines in FIGS. 5-16 represent theconnection from a fourth router in a first cluster to a fourth router ineach one of the other clusters.

FIG. 5 illustrates an example embodiment of a logical topology used forsystems having 129 processors to 160 processors. The logical topologycomprises three clusters 502, 504, 506 interconnected with twometarouters 508, 510. In an alternate embodiment, a single multiportmetarouter is used instead of the two metarouters 508, 510. In theexample embodiment, a first cluster 502 comprises sixty-four processorsand the second cluster 504 also comprises sixty-four processors. Thethird cluster 506 can include any number of processors from one tothirty-two making a total of 129 to 160 processors in the multiprocessorcomputer system shown in FIG. 5.

A router in each one of the three clusters 502, 504, 506 is connected toanother router in each one of the other three clusters 502, 504, 506through the metarouters 508, 510. Dashed lines represent the connectionbetween a first router in a first cluster and a single router in eachone of the other clusters. The first router 512 in a first cluster 502is connected to a first router 520 in a second cluster 504 through ametarouter 508. The first router 512 in the first cluster 502 is alsoconnected to a first router 530 in a third cluster 506 through themetarouter 508.

Likewise, the solid lines represent the connection between a secondrouter in the first cluster with a second router in each one of theother clusters. The second router 514 in the first cluster 502 isconnected to a second router 522 in the second cluster 504 through ametarouter 510. The second router 514 in the first cluster 502 is alsoconnected to a second router 532 in third cluster 506 through metarouter510.

Similarly, the dotted lines represent the connection between a thirdrouter in the first cluster with a third router in each one of the otherclusters and dash/dot lines in the diagrams represent the connectionbetween a fourth router in the first cluster with a fourth router ineach one of the other clusters. The third router 516 and the fourthrouter 518 in the first cluster 502 are directly connected to a thirdrouter 524 and a fourth router 528 in the second cluster 504. The thirdcluster 506 lacks a third router and a fourth router in thisconfiguration. Thus, as shown in FIG. 5, each one of the routers in acluster communicates with a router in each of the other clusters througheither a direct connection or through one or more metarouters. Thiseliminates the dependancy of one cluster to communicate with anothercluster through a third cluster and thus creates a more resilientsystem. The topologies of the present invention allow clusters tocommunicate directly with each other without communicating through athird cluster.

FIG. 6 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having 161 processors to 192 processors.The logical topology comprises three clusters 602, 604, 606interconnected with four metarouters 608, 609, 610, and 611. In analternate embodiment, two multiport metarouters are used in place of thefour metarouters 608, 609, 610 and 611. In the example embodiment shownin FIG. 6, a first cluster 602 comprises sixty-four processors and asecond cluster 604 also comprises sixty-four processors. A third cluster606 can include any number of processors from thirty-three processors tosixty-four processors for a total of 161 to 192 processors in themultiprocessor computer system shown in FIG. 6.

A router in each one of the three clusters 602, 604, 606 is connected toanother router in each one of the other three clusters 602, 604, 606through the metarouters 608, 609, 610 and 611. The first router 612 in afirst cluster 602 is connected to a first router 620 in a second cluster604 through a metarouter 608. The first router 612 in the first cluster602 is also connected to a first router 630 in a third cluster 606through the metarouter 608. Connections between the first router 612 inthe first cluster 602 and each one of the other clusters are representedin FIG. 6 with dashed lines.

Likewise, the second router 614 in the first cluster 602 is connected toa second router 622 in the second cluster 604 through a metarouter 610.The second router 614 in the first cluster 602 is also connected to asecond router 632 in third cluster 606 through metarouter 610.Connections between the second router 614 in the first cluster 602 andeach one of the other clusters are represented in FIG. 6 with solidlines. Similarly, the dotted lines in FIG. 6 represent the connectionsbetween a third router 616 in the first cluster 602 and each one of theother clusters. The third router 616 in the first cluster 602 isconnected to a third router 624 in the second cluster 604 throughmetarouter 609. The third router 616 in the first cluster 602 is alsoconnected to a third router 634 in the third cluster 606 throughmetarouter 609. Additionally, the dash/dot lines in FIG. 6 represent theconnections between a fourth router 618 in the first cluster 602 andeach one of the other clusters. The fourth router 618 in the firstcluster 602 is connected to a fourth router 628 in the second cluster604 through metarouter 611. The fourth router 618 in the first cluster602 is also connected to a fourth router 636 in the third cluster 606through metarouter 611. Thus, as shown in FIG. 6, each one of therouters in a cluster communicates with a router in each of the otherclusters through metarouters.

FIG. 7 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having 193 processors to 224 processors.The logical topology comprises four clusters 702, 704, 706, 707interconnected with four metarouters 708, 709, 710, and 711. In analternate embodiment, two multiport metarouters are used in place of thefour metarouters 708, 709, 710, and 711. In the example embodiment shownin FIG. 7, a first cluster 702, a second cluster 704, and a thirdcluster 706 each comprise sixty-four processors. A fourth cluster 707includes any number of processors from one processor up to thirty-twoprocessors for a total of 193 to 224 processors in the multiprocessorcomputer system shown in FIG. 7.

A router in each one of the four clusters 702, 704, 706, 707 isconnected to another router in each one of the other four clusters 702,704, 706, 707 through one of the metarouters 708, 709, 710 and 711.Connections between the first router 712 in the first cluster 702 andeach one of the other clusters are represented in FIG. 7 with dashedlines. The first router 712 in a first cluster 702 is connected to afirst router 720 in a second cluster 704 through a metarouter 708. Thefirst router 712 in the first cluster 702 is also connected to a firstrouter 730 in a third cluster 706 through the metarouter 708. Inaddition, as shown in FIG. 7, the first router 712 in the first cluster702 is connected to a first router 738 in a fourth cluster 707 throughthe metarouter 708.

Connections between the second router 714 in the first cluster 702 andeach one of the other clusters are represented in FIG. 7 with solidlines. The second router 714 in the first cluster 702 is connected to asecond router 722 in the second cluster 704 through a metarouter 710.The second router 714 in the first cluster 702 is also connected to asecond router 732 in third cluster 706 through metarouter 710Additionally, in FIG. 7 the second router 714 in the first cluster 702is connected to a second router 740 in a fourth cluster 707 through themetarouter 708.

Similarly, the dotted lines in FIG. 7 represent the connections betweena third router 716 in the first cluster 702 and each one of the otherclusters. The third router 716 in the first cluster 702 is connected toa third router 724 in the second cluster 704 through metarouter 709. Thethird router 716 in the first cluster 702 is also connected to a thirdrouter 734 in the third cluster 706 through metarouter 709. Likewise,the dash/dot lines in FIG. 7 represent the connections between a fourthrouter 718 in the first cluster 702 and each one of the other clusters.The fourth router 710 in the first cluster 702 is connected to a fourthrouter 728 in the second cluster 704 through metarouter 711. The fourthrouter 710 in the first cluster 702 is also connected to a fourth router736 in the third cluster 706 through metarouter 711.

Thus, as shown in FIG. 7, each one of the routers in a clustercommunicates with a router in each of the other clusters throughmetarouters. Furthermore, the 224 processor system shown in FIG. 7 iseasily created by expanding the 192 processor system shown in FIG. 6.First, the multiprocessor system of FIG.7 is formed by adding the fourthcluster 707. Second, the interconnections are added from the metarouter708 to a first router 738 in the fourth cluster 707. Third, theinterconnections are added from the metarouter 710 to the second router740 in a fourth cluster 707. Thus, a 192 processor system of the presentinvention is expandable to a 224 processor system without having torecable the first, the second, and the third clusters 702, 704, 706 toexpand the configuration.

FIG. 8 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having 225 processors to 256 processors.The logical topology comprises four clusters 802, 804, 806, 807interconnected with four metarouters 808, 809, 810, and 811. In theexample embodiment shown in FIG. 8, a first cluster 802, a secondcluster 804, and a third cluster 806 each contain sixty-four processors.In addition, the fourth cluster 807 can include from thirty-threeprocessors up to sixty-four processors for a total of 225 to 256processors in the multiprocessor computer system shown in FIG. 8.

A router in each one of the four clusters 802, 804, 806, 807 isconnected to another router in each one of the other four clusters 802,804, 806, 807 through one of the metarouters 808, 809, 810 and 811.Connections between the first router 812 in the first cluster 802 andeach one of the other clusters are represented in FIG. 8 with dashedlines. The first router 812 in a first cluster 802 is connected to afirst router 820 in a second cluster 804 through a metarouter 808. Thefirst router 812 in the first cluster 802 is also connected to a firstrouter 830 in a third cluster 806 through the metarouter 808. The firstrouter 812 in the first cluster 802 is also connected to a first router838 in a fourth cluster 807 through the metarouter 808.

Connections between the second router 814 in the first cluster 802 andeach one of the other clusters are represented in FIG. 8 with solidlines. The second router 814 in the first cluster 802 is connected to asecond router 822 in the second cluster 804 through a metarouter 810.The second router 814 in the first cluster 802 is also connected to asecond router 832 in third cluster 806 through metarouter 810, and thesecond router 814 in the first cluster 802 is connected to a secondrouter 840 in a fourth cluster 807 through the metarouter 808.

Similarly, the dotted lines in FIG. 8 represent the connections betweena third router 816 in the first cluster 802 and each one of the otherclusters. The third router 816 in the first cluster 802 is connected toa third router 824 in the second cluster 804 through metarouter 809. Thethird router 816 in the first cluster 802 is also connected to a thirdrouter 834 in the third cluster 806 through metarouter 809.Additionally, the 224 processor system of FIG. 7 is expanded in FIG. 8by adding a processing element node and a third router 842 in the fourthcluster 807 and connecting the third router 816 in the first cluster 802to the third router 842 in the fourth cluster 807 through metarouter809.

Likewise, the dash/dot lines in FIG. 8 represent the connections betweena fourth router 818 in the first cluster 802 and each one of the otherclusters. The fourth router 818 in the first cluster 802 is connected toa fourth router 828 in the second cluster 804 through metarouter 811.The fourth router 818 in the first cluster 802 is also connected to afourth router 836 in the third cluster 806 through metarouter 811.Additionally, the 224 processor system of FIG. 7 is further expanded inFIG. 8 by adding a processing element node and a fourth router 844 andconnecting the fourth router 818 in the first cluster 802 to the fourthrouter 844 in the fourth cluster 807 through metarouter 811.

Again, as shown in FIG. 8, each one of the routers in a clustercommunicates with a router in each of the other clusters throughmetarouters. Furthermore, the 256 processor system shown in FIG. 8 iseasily created by expanding the 224 processor system shown in FIG. 7.Thus, a 224 processor system of the present invention is expandable to a256 processor system merely by adding processing element nodes,interconnections, and routers to the fourth cluster 807. The expansionof the system does not require reconfiguration or recabling the first,the second, or the third clusters 702, 704, 706 in FIG. 7.

FIGS. 9-16 illustrate example embodiments of multiprocessor systemshaving greater than 256 processors. The multiprocessor systems shown inFIGS. 9-16 are built by expanding the configuration shown in FIG. 8comprising up to 256 processors. The 256 processor system shown in FIG.8 has four clusters configured as 2D hypercubes and interconnected withmetarouters. According to the present invention, multiprocessor systemshaving more than 256 processors are configured by adding clusters to theconfiguration shown in FIG. 8 and connecting each one of the clusters tothe other clusters in the configuration by one or more metarouters.

FIG. 9 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 288 processors. The 288processor system shown in FIG. 9 is easily created by expanding the 256processor system shown in FIG. 8. A fifth cluster 962 is added to themultiprocessor system and two additional metarouters 950, 952 are addedto the multiprocessor system. Interconnections are added from themetarouter 950 to a first router 970 in the fifth cluster 962, and toanother metarouter. Interconnections are also added from the metarouter952 to a second router 972 in the fifth cluster 962, and to anothermetarouter. Thus, a 256 processor system of the present invention iseasily expandable to a 288 processor system without having toreconfigure the original 256 processor system.

FIG. 10 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 320 processors. The 320processor system shown in FIG. 10 is easily created by expanding the 288processor system shown in FIG. 9. A sixth cluster 1064 is added to themultiprocessor system. Interconnections are added from the metarouter1050 to a first router 1078 in the sixth cluster 1064. Interconnectionsare also added from the metarouter 1052 to a second router 1080 in thesixth cluster 1064. As shown in FIG. 10, a 288 processor sysem of thepresent invention is easily expandable to a 320 processor system withouthaving to reconfigure the original 288 processor system.

FIG. 11 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 352 processors. The 352processor system shown in FIG. 11 is easily created by expanding the 320processor system shown in FIG. 10. A third router 1174 (and acorresponding processor element node) and a fourth router 1176 (and acorresponding processor element node) are added to the fifth cluster1162 of the multiprocessor system. Interconnections are added from themetarouter 1154 (which is also added to the multiprocessor system) tothe third router 1174 in the fifth cluster 1162. Interconnections arealso added from the metarouter 1156 (which is also added to the system)to the fourth router 1176 in the fifth cluster 1162. The new metarouters1154, 1156 are also interconnected to the previous metarouters. As shownin FIG. 1, a 320 processor sysem of the present invention is easilyexpandable to a 352 processor system without having to reconfigure theoriginal 320 processor system.

FIG. 12 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 384 processors. The 384processor system shown in FIG. 12 is easily created by expanding the 352processor system shown in FIG. 1. A third router 1282 and a fourthrouter 1284 and the corresponding processing element nodes are added tothe sixth cluster 1264 of the multiprocessor system. Interconnectionsare added from the metarouter 1254 to the third router 1282 in the sixthcluster 1264. Interconnections are also added from the metarouter 1256to the fourth router 1284 in the sixth cluster 1264. As shown in FIG.12, a 352 processor sysem of the present invention is easily expandableto a 384 processor system without having to reconfigure the original 352processor system.

FIG. 13 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 416 processors. The 416processor system shown in FIG. 13 is easily created by expanding the 384processor system shown in FIG. 12. A seventh cluster 1386 having a firstrouter 1388 and a second router 1389 are added to the multiprocessorsystem. Two metarouters 1355, 1357 are also added. Interconnections areadded from the metarouter 1355 to the first router 1388 in the seventhcluster 1386 and to one of the metarouters. Interconnections are alsoadded from the metarouter 1357 to the second router 1389 in the seventhcluster 1386 and to one of the other metarouters. As shown in FIG. 13, a384 processor sysem of the present invention is easily expandable to a416 processor system without having to reconfigure the original 384processor system.

FIG. 14 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 448 processors. The 448processor system shown in FIG. 14 is easily created by expanding the 416processor system shown in FIG. 13. An eighth cluster 1487 having a firstrouter 1492 (and corresponding processing element node) and a secondrouter 1493 (and corresponding processing element node) are added to themultiprocessor system. Interconnections are added from the metarouter1455 to the first router 1492 in the eighth cluster 1487.Interconnections are also added from the metarouter 1457 to the secondrouter 1493 in the eighth cluster 1487. As shown in FIG. 14, a 416processor sysem of the present invention is easily expandable to a 448rocessor system without having to reconfigure the original 416 processorsystem.

FIG. 15 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 480 processors. The 480processor system shown in FIG. 15 is easily created by expanding the 448processor system shown in FIG. 14. A third router 1590 and a fourthrouter 1591 are added the seventh cluster 1586 of the multiprocessorsystem. Two metarouters are also added 1558, 1559 and interconnectionsare added from the two metarouters 1558, 1559 to another metarouter.Interconnections are added from the metarouter 1558 to the third router1590 in the seventh cluster 1586. Interconnections are also added fromthe metarouter 1559 to the fourth router 1591 in the seventh cluster1586. As shown in FIG. 15, a 448 processor sysem of the presentinvention is easily expandable to a 480 processor system without havingto reconfigure the original 448 processor system.

FIG. 16 illustrates an example embodiment of a logical topology used formultiprocessor computer systems having up to 512 processors. The 512processor system shown in FIG. 16 is easily created by expanding the 480processor system shown in FIG. 15. A third router 1694 (and acorresponding processing element node) and a fourth router 1695 (and acorresponding processing element node) are added the eighth cluster 1687of the multiprocessor system. Interconnections are added from themetarouter 1658 to the third router 1694 in the eighth cluster 1687.Interconnections are also added from the metarouter 1659 to the fourthrouter 1695 in the eighth cluster 1687. As shown in FIG. 16, a 480processor sysem of the present invention is easily expandable to a 512processor system without having to reconfigure the original 480processor system.

FIG. 17 illustrates an example embodiment of a system according to FIG.16. Each router (19, 27) is connected to four compute nodes (Cbricks).The remaining four ports are connected to other routers. Router 38provides between routers, routers 27 and other routers 38.

The present invention, as described above, permits smaller systems to beexpanded to larger systems with minimal disruption to the originalsystem configuration. Although specific embodiments have beenillustrated and described herein for purposes of description of thepreferred embodiment, it will be appreciated by those of ordinary skillin the art that a wide variety of alternate and/or equivalentimplementations calculated to achieve the same purposes may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. Those with skill inthe mechanical, electro-mechanical, electrical, and computer arts willreadily appreciate that the present invention may be implemented in avery wide variety of embodiments. This application is intended to coverany adaptations or variations of the preferred embodiments discussedherein. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

1. A massively parallel processing system comprising: a plurality ofprocessing element nodes; a scalable interconnection network comprising:a plurality of physical communication links; and a plurality of firstlevel routers for interconnecting the plurality of processing elementnodes in a cluster; and one or more metarouters for interconnecting theplurality of first level routers so that each one of the routers in afirst cluster is connected to all other clusters through one or moremetarouters.
 2. The massively parallel processing system of claim 1wherein each one of the clusters is a two-dimensional hypercube.
 3. Themassively parallel processing system of claim 1 wherein each one of themetarouters are eight port routers.
 4. The massively parallel processingsystem of claim 1 wherein each one of the metarouters are four portrouters.
 5. The massively parallel processing system of claim 1 whereineach one of the processing element nodes comprises four processors.
 6. Amassively parallel processing system comprising: a plurality ofprocessors; a first set of routers for interconnecting the plurality ofprocessors as two-dimensional hypercubes; and a second set of routersfor interconnecting the first set of routers wherein the hypercubesremain in tack as the system is expanded.